High-speed serial interfaces such as CEI, XFP/XFI, 10-Gbit/s Ethernet, and both 4-Gbit/s and 10-Gbit/s Fibre Channel are creating demands for test equipment that can give you detailed performance ...

Signal integrity is a critical design consideration in modern electronic systems, particularly those that depend on high-speed interconnects. As data rates climb and interconnect geometries become ...

Electronics design trends that ratchet updesign complexity and speed, such as theuse of multiple high-speed buses, bring newsignal-integrity challenges. With that inmind, EDN assembled a virtual panel ...

Agilent Technologies Inc. introduced the oscilloscope industry's first eye-diagram mask testing capability for the differential Controller Area Network (CAN) serial bus. The CAN serial bus is used ...

The most different aspect between a normal lamination structure and High-Density Fan-out (HDFO) is the routing scale. That aspect is also the challenge and focus of this study. At an HDFO scale, most ...

Double-data-rate synchronous dynamic random access memory (DDR SDRAM) physical-layer testing is a crucial step in making sure devices comply with the JEDEC specification. The ultimate goal is to ...

Connecting an application processor to a DRAM chip through a 3200 Mbps LPDDR4 interface is not any easier than routing a 2600 MHz 4G LTE antenna. While RF front ends enjoy ceramic packages and careful ...