EDN

Leveraging system models for RTL functional verification

Register transfer level (RTL) verification remains the bottleneck in digital hardware design. Industry surveys show that functional verification accounts for 70 percent of the total design effort. Yet ...
EDN

How to raise the RTL abstraction level and design conciseness with SystemVerilog – Part 1

With the advent of advanced HDLs – such as SystemVerilog – that provide new and powerful language constructs, current hardware modeling styles can now be enhanced both in terms of abstraction level ...
Electronic Design

In Adding Control-Logic Support, A High-Level Synthesis Tool Goes Full Chip

High-level synthesis (HLS), or the notion of synthesizing a design into RTL from a higher level of abstraction, has been gaining currency among design teams. For some time now, there have been ...
Design-Reuse

Virage Logic Delivers Open RTL to Test Floor Embedded Memory Test and Repair Subsystem

New Release of STAR Memory System Expands Availability of Subsystem Beyond Virage Logic Memories to Third-Party and Internally Developed Memories FREMONT, Calif. -- June 2, 2008 -- Virage Logic ...
Opinion
Printed Circuit Design & Fab Online MagazineOpinion

A Novel Synthesis Approach for Simplifying PCB Design

A new logic-level approach directly impacts board-level performance and complexity. By optimizing interconnects, fanouts and signal structures before schematic capture, a new gate-level synthesis ...
Design-Reuse

A Method and Approach for Fast and Efficient Debugging at Emulation Level

Advancement of technology has transformed big and complex circuit boards into small and simple Integrated Chips (ICs). ICs have surpassed circuit boards in every field. Be it their small size, lower ...
Business Wire

Cadence Unveils Joules RTL Design Studio, Delivering Breakthrough Gains in RTL Productivity and Quality of Results

Delivers up to 5X faster RTL convergence and up to 25% improved QoR RTL designers can rapidly get accurate insight into physical effects and actionable guidance on improving RTL Integrates with ...
Electronic Design

Programmable Logic: To HDL Or Not To HDL?

Engineers grappling with FPGA design have new EDA tools ready to reclaim time-to-design completion. Strategies for EDA tool usage will change course as gate levels, and ultimately costs, rise in ...
Semiconductor Engineering

Shift Left In DFT Design

The semiconductor industry continues to face numerous challenges as designs approach reticle limits, process nodes evolve and engineering resources become increasingly stretched. It is essential to ...
Semiconductor Engineering

How To Manage DFT For AI Chips

Semiconductor companies are racing to develop AI-specific chips to meet the rapidly growing compute requirements for artificial intelligence (AI) systems. AI chips from companies like Graphcore and ...