For over 15 years, I've been a big proponent of hierarchical test. Hierarchical test is the commonly used term for creating DFT (design-for-test) features and test patterns at lower level circuit ...

The old adage “time is money” is highly applicable to the production testing of semiconductor devices. Every second that a wafer or chip is under test means that the next part cannot yet be tested.

Test compression sounds like magic. Read on to learn how this trick is done. Large, complex ICs are viable because their design meets test as well as functional requirements. Design for test (DFT) was ...

Design for testability (DFT) works to make a circuit more testable to ensure that it was manufactured correctly. Alfred Crouch explains the purpose of DFT in his book, Design-For-Test for Digital ICs ...

When you purchase through links on our site, we may earn an affiliate commission. Here’s how it works. The Sarnoff Digital Test Pattern When I was approached about evaluating the Sarnoff Digital Test ...