EDN

Test-bench generation tool simplifies IC design

TestBencher Pro VHDL and Verilog system-level test-bench generation software is said to dramatically simplify the process of creating and applying random bus transactions to RTL and gate-level IC and ...
Electronic Design

Development Environment Supports Mixed C++ And HDL Test Benches

TestBencher Pro v8.0 adds support for mixed C++ and hardware description language (HDL) test benches using the open standard TestBuilder library. This library offers useful verification capabilities, ...
Design-Reuse

Automatic C-to-VHDL testbench generation shortens FPGA development time

Verifying behavior early and often has become critical with FPGAs. Newer generations of FPGAs have gate counts that rival the largest custom ASICs of five years ago. This fact, coupled with the broad ...
Electronic Design

The MathWorks App Generates HDL Code From System Models

The Simulink HDL Coder automatically generates synthesizable hardware description language (HDL) code from models created in the company’s Simulink and Stateflow software. It produces ...
EDN

Design package generates HDL from system models

Providing automatic synthesis of software code to an ASIC or FPGA from system models created in the widely-used Simulink simulation and model-based design tool, Simulink HDL Coder is presented as a ...