A new logic-level approach directly impacts board-level performance and complexity. By optimizing interconnects, fanouts and signal structures before schematic capture, a new gate-level synthesis ...

Here is a fork of ABC containing Agdmap, a novel technology mapper for LUT-based FPGAs. Agdmap is based on a technology mapping algorithm with adaptive gate decomposition [1]. It is a cut enumeration ...

I was wondering if it was possible to exclude a net from clock tree synthesis even if it is combinatorially connected to the root clk? An example would be if the clock was used to generate a pulse ...

ABSTRACT: The production of polyhydroxyalkanoate (PHA) is an opportunity to gradually replace some plastics produced from fossil resources. The use of agro-industrial waste to produce PHA is one of ...

Ternary reversible logic is a promising choice for low-power implementation and is also physically realizable in quantum computation. Two previous methods for ternary reversible circuit synthesis are ...

Members can download this article in PDF format. For market growth to occur at desired levels, suppliers must meet consumer demand for compact electronic devices that integrate multiple functions. To ...

As I mentioned in my recent columns on the topic of adding pull-up or pull-down resistors to the inputs of unused or partially used logic gates and functions (see Part 1, Part 2, and Part 3), I was ...

Abstract: This work aims to optimize the superconducting single flux quantum (SFQ) combinational logic synthesis process to cope with the scaling up of superconducting SFQ integration. The majority of ...